Spacecraft Onboard Data Handling Projects

Research projects on spacecraft onboard data handling that the Space Technology Centre has either led or had a significant role in are described below:

Advanced Payload Processing

The ESA Advanced Payload Processing study aimed to develop a highly modular payload processing architecture for use on future satellites. The Space Systems Research Group at Dundee provided consultancy support to the prime contractor Dornier Satellitensysteme (now Astrium GmbH) for this study in the areas of multi-processor DSP systems and routing switch architectures for SpaceWire.

SpaceWire CODEC Support

The SpaceWire CODEC Support project is aimed to provide updates and support for end users of the SpaceWire CODEC IP. The IP is a synthesisable VHDL model of the SpaceWire data strobe encoder decoder maintained by the University of Dundee, originally developed under the SpaceWire router ASIC project.

SpaceWire Router ESM006

Details coming soon.

SpaceWire-10X Testing

The aim of the SpaceWire-10X Testing project is to test the SpaceWire-10X Router ASIC device under various conditions to ensure there are no problems with the device. This involves the development of a test environment in which it is possible to stress the SpW-10x's operation. Appropriate tests have been devised and these will be performed and the results analysed.

SpaceWire CODEC IP - Actel Implementation

The SpaceWire CODEC IP Actel implementation is an ESA managed project to provide an implementation of the SpaceWire CODEC IP VHDL model to the Actel RTAX and RTSX FPGA series devices. The Actel RTAX and RTSX devices are radiation tolerant versions of the AX and SX commercial FPGAs which provide protection against single event effects (SEE). RTAX and SX devices use anti-fuse (program once) technology, are protected from single event latch-up (SEL) and implement triple mode redundancy for each internal flip-flop to protect against single event upsets (SEU).

Real-Time Embedded CORBA over SpaceWire (RECS)

To investigate effective DSP processor to SpaceWire integration, the University of Dundee has developed a DSP board using one of the latest DSP processors from Analog Devices and a SpaceWire router. The SpaceWire DSP board comprises an eight-port SpaceWire router connected to an Analog Devices 21160 SHARC (Super-Harvard ARChitecture) DSP processor. The 21160 processor has six SHARC links which are high-speed, half-duplex, bi-directional, point-to-point communication links designed to connect together several SHARC processors in a parallel processing array. These links form the bridge between the SHARC processor and the SpaceWire router. Data to be sent out from the DSP processor are formed into SpaceWire packets with an appropriate destination address header and the cargo (i.e. the data to be sent in the packet). The packet is then transmitted across the SHARC link to the SpaceWire router with an end of packet marker code being appended to the packet. Data is received in a similar way with the SpaceWire packet being transferred across the SHARC link.

SpaceWire Router ETD031

Details coming soon.

SpaceFibre

Details coming soon.

RMAP Standard

Details coming soon.